Memory modules can be characterized by form factor. The form factor for any memory module describes its size and pin configuration. An example of an older form factor for memory modules is the SIMM type, where SIMM is an acronym for single in-line memory module. A newer form factor is the DIMM type, where DIMM is an acronym for dual in-line memory module. There are several variations of DIMMs, with new variations continuing to evolve.
FIG. 1A is a cross-section of a DIMM 100, according to the Background Art, taken along section line IA-IA′ shown in FIGS. 1B and 1C.
DIMM 100 includes: a printed circuit board (PCB) 102; and integrated circuit memory devices 104—i (e.g., 104_1, 104_2, 104_3 and 104_4). Typically, the integrated circuit memory devices are packaged devices, each of which contains one or more integrated circuit chips. For example, the packaged devices may be in form of plastic leaded packages, BGA (ball grid array) packages, and WFPs (wafer-level fabricated packages), etc. It is assumed in FIG. 1A that the integrated circuit memory devices are in form of BGA packages. PCB 102 has a front side 130 and a back side 132. Conductive segments (hereafter referred to as wires) are printed on front side 130 and back side 132 of PCB 102. More particularly, wires 116, 118, 124 and 126 are visible in FIG. 1A on front side 130 of PCB 102, and wires 114, 120, 122 and 128 are visible in FIG. 1A on back side 132 of PCB 102. The vias are formed in PCB 102, of which vias 108_6 and 110_7 are visible in FIG. 1A. Conductive terminals 106 of memory devices 104—i, e.g. conductive balls in the circumstance of a BGA package, connect conductive I/O terminals of the circuits (not shown) in memory devices 104—i to the various wires on PCB 102.
Relative to a reference axis, e.g., the longitudinal axis of PCB 102, memory devices 104_1 and 104_2 align at a first reference location so as to overlap each other. Similarly, memory devices 104_3 and 104_4 align at a second reference location so as to overlap each other. To simplify description, memory devices 104_1 & 104_2 will be referred to as positional-twins. Similarly, memory devices 104_3 and 104_4 will be referred to as positional-twins.
FIG. 1B is a front view of the printed wires and vias of PCB 102 that fall within the overlying footprints 134 of memory devices 104_1 and 104_2, according to the Background Art. FIG. 1C is a front view of the printed wires and vias of PCB 102 that fall within the overlying footprints 136 of memory devices 104_3 and 104_4, according to the Background Art.
In FIG. 1B, vias 108_1, 108_2, . . . , 108_4 are called out. Similarly, in FIG. 1C, vias 110_1, 110_2, . . . , 110_4 are called out. In FIGS. 1B and 1C, wires on front side 130 of PCB 102 as well as wires on back side 132 of PCB 102 are visible. For simplicity of illustration, however, only wires 114, 116, 122 and 124 are called out in FIGS. 1B and 1C, respectively. A fuller understanding of FIGS. 1B & 1C can be facilitated with reference to FIGS. 2A-2C.
FIG. 2A is a front view of the printed wires and vias on front side 230 of a PCB (not depicted) in a DIMM (not depicted) that fall within the overlying footprint of a memory device (not depicted), according to the Background Art. FIG. 2B is a back-side view of the printed wires and vias on a back side 232 of the same PCB in the same DIMM that fall within the overlying footprint of a positional-twin memory device (not depicted), according to the Background Art. FIG. 2C is a front view of the printed wires and vias of the PCB that fall within the overlapped footprints of the positional-twin memory devices, according to the Background Art. FIGS. 2A-2C (again) are provided to help relate FIGS. 1B and 1C to FIG. 1A.
A description of how FIG. 2C is obtained can be as follows: rotate FIG. 2B 180° about a flip axis 24; and then superimpose FIG. 2A upon the rotated version of FIG. 2B. Alternatively, a description of how FIG. 2C is obtained can be as follows: make a left-hand rotation of FIG. 2A about a fold axis 26 and make a right-hand rotation of FIG. 2B about fold axis 26, bringing FIG. 2A toward FIG. 2B as one might close a book or fold a sheet of paper; and then make a right-hand rotation of the closed-book/folded-sheet until the wires in the closed-book/folded-sheet corresponding to the wires in FIG. 2A have the same orientation as in FIG. 2A.
In FIG. 2C, vias 11 and 12 connect wires 16 & 20 and 22 & 18, respectively. Pads 1a and 1b′ (or, in other words, end portions) of wires 16 and 22, respectively, are not electrically connected, but they do overlap (again, given the relationship of FIG. 2C to FIGS. 2A-2B). Hence, in FIG. 2C, one circle encloses both reference numbers 1a and 1b′. Similarly, pads 1a′ and 1b of wires 20 and 18, respectively, are not electrically connected, but they do overlap. Accordingly, in FIG. 2C, one circle encloses both reference numbers 1a′ and 1b. 
Returning to FIGS. 1A-1B, conductive terminals 106 can be described as being clustered along opposing edges of each memory device 104—i. In contrast and relative to the arrangement of conductive terminals 106, vias 108—i can be described as being clustered along a central axis of each memory device 104—i. 